The invention relates to a semiconductor device comprising a semiconductor chip stack and a method for producing the same. Semiconductor devices of this type have at least one lower semiconductor chip as base of the semiconductor chip stack and at least one upper semiconductor chip. In this case, the semiconductor chips are stacked directly one on top of another. In the case of conventional stacking of this type it must be ensured that the individual potentials of the semiconductor chips are effectively insulated from one another during the stacking.
Electrical insulation, however, is detrimental to the thermal conductivity. Thus, by way of example, when a logic chip is fixed onto a transistor by means of an insulating adhesive, thermal conductivity is adversely affected. This is because an increased thermal resistance forms on the top side of the lower semiconductor chip, which forms the base, as a result of an upper stacked semiconductor chip being applied by adhesive bonding. In addition, the size of the upper semiconductor chip is disadvantageously limited with regard to its areal extent since it cannot project beyond the edge of the lower semiconductor chip without increasing the risk of the semiconductor chip stack breaking.
Furthermore as a result of semiconductor chips being adhesively bonded onto one another to form a semiconductor chip stack, a redistribution wiring between the electrodes of the semiconductor chips that are adhesively bonded onto one another, namely those on the top side of the lower semiconductor chip and those on the rear side of the upper semiconductor chip, is not possible without considerable outlay in terms of costs. Power semiconductor chips having electrodes on the top side and the rear side cannot therefore be stacked satisfactorily by means of adhesive bonding technology. In the case of semiconductor chips of this type it is only possible for electrodes that are of identical type and equal in area, that is to say congruent, to be adhesively bonded onto one another by means of a conductor adhesive, such that in circuitry terms only restricted functions can be realized by means of a stacking.
Moreover, it is possible, in the context of “wafer level packaging technology” to electrically connect two composite plates with corresponding embedded semiconductor chips and with wiring structures on coplanar top sides via through contacts in such a way that a semiconductor device comprising a semiconductor chip stack arises, the semiconductor chips of which are electrically wired to one another via vertical through contacts and horizontal wiring structures. Such stacking of semiconductor chips is not advantageous for stacking power semiconductor chips on account of the thermal insulation of the semiconductor chip stack, even though the wiring possibilities are improved.
Furthermore, it is possible to create multilayered ceramic substrates which can be equipped with semiconductor chips on both sides, such that the heat-loss-generating top sides of the semiconductor chips are uncovered on both sides of the substrate plate and can dissipate heat. However, this requires a substrate technology having a high material outlay.
Finally, it is also possible to provide semiconductor chips with a sequence of metallization and insulation layers on the areas with which they are intended to be connected, and then to adhesively bond them onto one another. Although this affords the possibility of complex wiring, the thermal effects are serious and not advantageous for power semiconductor devices.
In light of the foregoing, there is a need for improved semiconductor chip stack configurations.